1. Field of the Invention
The present invention relates generally to a semiconductor memory device having a delay locked loop and, more particularly, to a delay locked loop voltage supply circuit.
2. Description of the Related Art
Large scale integrated circuits such as semiconductor memory devices, particularly double data rate synchronous DRAM semiconductor devices, may include a delay locked loop to reduce skew between clock signals or between a clock signal and data. However. delay locked loops are sensitive to noise introduced by the power supply. One solution to this problem is to include a direct current voltage generator as an internal power voltage generator and reference voltage generator on the semiconductor memory device, dedicated to the delay locked loop.
However, in low frequency applications, where the problem of skew between clock signals and data is reduced, it is desirable to turn the delay locked loop off. In a semiconductor device with a delay locked loop and a direct current voltage generator as described above, the direct current voltage generator continues to operate even when the delay locked loop is not in use, causing unnecessary power consumption.